The present invention generally relates to semiconductor devices, and particularly to forming gate dielectric layers of n-type field effect transistors (nFETs) and p-type field effect transistors (pFETs).
Metal-oxide-semiconductor (MOS) technology is a commonly used technology for fabricating field effect transistors (FETs) as part of advanced integrated circuits, such as CPUs, memory, and storage devices, and the like. In MOS technology, a FET may be formed by depositing a gate structure over a channel region connecting a source and a drain. For planar FETs, the channel region is formed in a semiconductor substrate on which the gate structure is formed. In finFETs, the gate structure may be formed over or around a semiconductor fin on an insulator layer, with a source and a drain formed on opposite ends of the semiconductor fin.
In MOS technology, the gate structure may be made of a gate dielectric and a gate electrode. In traditional MOS-FETs, the gate dielectric consists of a silicon dioxide layer intended in part to prevent current from leaking from the gate electrode into the channel. However, as the critical dimensions of modern microelectronic structures continues to decrease, silicon dioxide gate dielectrics may not be reliably used as gate dielectrics. Therefore, an increasing trend in microelectronic devices is to at least partially replace the silicon dioxide gate dielectric with a high-k dielectric, such as tantalum oxide, strontium titanium oxide, hafnium oxide, hafnium silicon oxide, aluminum oxide or zirconium oxide. These high-k dielectrics may be reliably fabricated with thicknesses much greater than an equivalent silicon dioxide layer while maintaining approximately the same ability to prevent leakage. Additionally, there has been a trend to replace the traditional doped polysilicon gate electrode with a metal gate electrode to reduce the effects of the poly gate depletion phenomenon.
However, the change to a high-k gate dielectric and/or a metal gate may result in sub-optimal threshold voltages, particularly in pFET devices. One method of readjusting the threshold voltages of FET devices is through the use of work-function metals, which may be diffused into the gate dielectric to adjust the threshold voltage of the FET. However, the ideal work-function metals for tuning the threshold voltage of a pFET device and nFET device may differ. Additionally, nitridation of the gate dialectic has proven to be an effective method of nFET devices. However, nitridation of a pFET gate dielectric may tune the threshold voltage of the pFET device away from optimal levels.
Therefore, a method of concurrently tuning gate dielectrics of nFET and pFET devices using different work-function metals while also selectively nitriding the gate dielectric of the nFET device is desirable.